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MIC25400 2a dual output pwm synchronous buck regulator ic ramp control is a trademark of micrel, inc. mlf and microleadframe are registered trademarks of amkor technology, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com january 2011 m9999-020111-c general description the MIC25400 is a synchronous pwm dual output step down converter with internal 2a high-side switches. the MIC25400 has an integrated low-side gate driver for synchronous step-down conv ersion by connecting an external n-channel mosfet to achieve high efficiencies in low duty-cycle applicat ions. the ic?s switching frequency is 1mhz. a patented control scheme allows the use of a wide range of output capacitance from small ceramic capacitors to large electrolytic types with only one compensation component. a 2% output voltage tolerance over the temperature range allows the maximum level of system performance. the MIC25400 power good signal allows full control for sequencing the output voltages with minimum external components. an adjustable current limit allows the use of smaller inductors in lower current applications. the MIC25400 is available in the epad 24-pin 4mm x 4mm mlf ? package, and has an operating junction temperature range of ?40 c to +125 c. features ? 4.5v to 13.2v input voltage range ? adjustable output voltages down to 0.7v ? 2a per channel ? 180 out of phase operation ? low-side driver for synchronous operation ? 2% output voltage accuracy (over temperature) ? 1mhz switching frequency ? output voltage sequencing ? programmable max current-limit ? power good output ? ramp control? provides soft-start ? low-side current sensing a llows very low duty-cycle ? works with ceramic output capacitors ? 24-pin 4mm x 4mm mlf ? package ? junction temperature range of ?40 c to +125 c applications ? multi-output power supplies with sequencing ? dsp, fpga, cpu and asic power supplies ? telecom and networking equipment, servers _________________________________________________________________________________________________________________________ typical application MIC25400 dual output buck converter
micrel, inc. MIC25400 january 2011 2 m9999-020111-c ordering information part number voltage switching frequency temperature range package lead finish MIC25400yml adj 1mhz -40 c to +125 c 24-pin 4mm x 4mm mlf ? pb-free pin configuration 24-pin 4mm x 4mm mlf ? (ml) pin description pin number pin name pin description 1 bst1 boost 1 (input): provides voltage for high-side internal mosfet for channel 1. connect a 0.01f capacitor from sw1 to bst1 pin and a diode-to-pvdd. 2 lsd1 low-side drive 1 (output): exte rnal low-side n-channel mosfet driver. use 4.5v rated mosfets. 3 pgnd1 power ground 1 (input). 4 cs1 current sense 1 (input): place a re sistor from sw1 to this pin to program the current limit point from 0.5a to 2.7a. 5 pg1 power good 1 (output): open drain. device is in the off state. i.e., high when output is within 90% of regulation. 6 en/dly1 enable/delay 1 (input): this pin can be used to disable v out1 . when used to disable v out1 , this pin must be pulled down to ground in less than 1s for proper operation. it is also used for soft-start of the output. soft start capacitor range is 4.7nf to 22nf. see the functional description section of this datasheet for additional information. 7 comp1 compensation 1 (input): pin fo r external compensation, channel 1. 8 fb1 feedback 1 (input): input to ch1 error amplifier. regulates to 0.7v. 9 nc no connect. 10 agnd analog ground (input): control sect ion ground. connect to pgnd. 11 fb2 feedback 2 (input): input to channe l 2 error amplifier. regulates to 0.7v. 12 comp2 compensation 2 (input): pin fo r external compensation, channel 2.
micrel, inc. MIC25400 january 2011 3 m9999-020111-c pin number pin name pin description 13 en/dly2 enable/delay 2 (input): this pin can be used to disable v out2 . when used to disable v out2 , this pin must be pulled down to ground in less than 1s for proper operation. it is also used for soft-start of the output. soft start capacitor range is 4.7nf to 22nf. see functional description section for additional information. 14 pg2 power good 2 (output) open drain. de vice is in the off state. i.e., high when output is within 90% of regulation 15 cs2 current sense 2 (input) place a resistor from sw2 to this pin to program the current limit point from 0.5a to 2.7a 16 pgnd2 power ground 2 (input) 17 lsd2 low-side drive 2 (output): exte rnal low-side n-channel mosfet driver. use 4.5v rated mosfets. 18 bst2 boost 2 (input): provides voltage for high-side internal mosfet for channel 2. connect a 0.01f capacitor from sw2 to bst2 pin and a diode-to-pvdd. 19 sw2 switch node 2 (output): source of internal high-side power mosfet. 20 vind2 supply voltage (input): for the drain of internal high-side power mosfet 4.5v to 13.2v. 21 pvdd 5v internal linear regulator (output ): pvdd is the external mosfet gate drive for lsd1 and lsd2 and an internal supply bus for the ic. connect to an external 1f bypass capacitor. when vin is <6v, this regulator operates in drop-out m ode. connect vdd to vin when vin <6v. 22 vin supply voltage (input): for the internal 5v linear regulator. 4.5v to 13.2v. 23 vind1 supply voltage (input): for the drain of internal high-side power mosfet 4.5v to 13.2v. 24 sw1 switch node 1 (output): source of internal high-side power mosfet. ep gnd exposed thermal pad for package only. connect to ground. must make a full connection to the ground plane to maximize thermal performance of the package.
micrel, inc. MIC25400 january 2011 4 m9999-020111-c absolute maximum ratings (1) v in to pgnd .................................................... ?0.3v to 16v v ind1 , v ind2 to pgnd........................................ ?0.3v to 16v v pvdd to pgnd .................................................. ?0. 3v to 6v v sw1 , v sw2 to pgnd ............................ ?0.7v to (v in + 0.3v) v cs1 , v cs2 to pgnd ............................. ?0.7v to (v in + 0.3v) v bst1 to v sw1 , v bst2 to v sw2 ............................ ?0.3v to 6.0v v bst1 , v bst2 to pgnd....................................... ?0.3v to 22v v en/dly1 , v en/dly2 to pgnd...............?0.7v to (v pvdd + 0.3v) v comp1 , v comp2 to pgnd..................?0.7v to (v pvdd + 0.3v) v fb1 , v fb2 to pgnd..........................?0.7v to (v pvdd + 0.3v) v pg1 , v pg2 to pgnd .........................?0.7v to (v pvdd + 0.3v) pgnd1, pgnd2 to agnd ........................... ?0.3v to +0.3v junction temper ature ................................................ 150c storage temper ature ...............................?65 c to +150 c lead temperature (solde ring,10 sec. )....................... 260c operating ratings (2) supply voltage (v in )................................... +4.5v to +13.2v output voltage range (v out )?????......0.7v to 0.7*v in maximum output current (i out )?????.. ................... 2a junction temperature (t j ) ........................ ?40c to +125c junction thermal resistance 4mm x 4mm mlf-24l ( ja ) ...............................35c/w electrical characteristics (4) v in = 12; v en =5v; v out =1.8v; i load =10ma; t a = 25c, bold values indicate ?40c t j +125c, unless noted. parameter condition min typ max units power input supply input voltage range (v in ) 4.5 13.2 v quiescent supply current v fb = 0.8v, i out = 0a; both outputs not switching 3.6 7 ma shutdown current v en1 = v en2 = 0v 360 425 a v in uvlo threshold v in rising, p vdd open, for v in 6v 3.6 4.02 4.5 v v in uvlo hysteresis v in 6v 150 mv v in uvlo v in <6v) v in rising, p vdd connected to v in , for v in <6v 3.2 3.5 3.9 v vdd supply internal bias voltages p vdd v fb = 0.8v, i pvdd = 75ma 4.7 5.1 5.4 v reference (each channel) feedback reference voltage 2% over temperature 686 700 714 mv fb bias current v fb = 0.7v 5 na fb line regulation v in = 6v to 13.2v, i ou t = 10ma 0.005 %/v output voltage line regulation v in = 6v to 13.2v , v out = 1.8v, i ou t = 1a 0.005 %/v output voltage load regulation v out = 1.8v, i ou t = 0a to 2a 0.15 % output voltage total regulation v in = 6v to 13.2v , i ou t = 0.25a to 2a, v out = 1.8v 0.1 % external current sense, adjustable current limit trip point current sourcing current 175 200 225 a current limit temperature coefficient 750 ppm/c current limit comparator offset -10 0 10 mv
micrel, inc. MIC25400 january 2011 5 m9999-020111-c parameter condition min typ max units oscillator / pwm switching frequency 0.8 1 1.2 mhz maximum duty-cycle 70 75 % minimum on-time i load > 200ma (5) 15 ns error amplifier (each channel) dc gain 68 db high-side internal mosfet on resistance rds(on) i fet = 1a, v fb =0.8v 150 m low-side mosfet driver pull up, i source = 10ma 4 dh on-resistance pull down; i sink = 10ma 2.5 into 1000pf 12 ns dh transition time into 1000pf 9 ns driver non-overlap dead time (adaptive) 25 ns en/dly and soft-start control en/dly pull-up current v en/dly =0v 5.0 6.5 8.0 a p vdd threshold p vdd turns on 0.3 0.4 0.6 v soft-start begins threshold channel soft-start begins 1 1.35 1.8 v soft-start ends threshold channel soft-start ends 2 2.4 2.8 v power good pg threshold voltage v out rising (% of v out nominal) 86 90 94 %nom pg output low voltage v fb = 0v, i pg = 1ma 0.24 0.3 v pg leakage current v fb = 800mv, v pg = 5.5v 5 na thermal protection over-temperature shutdown t j rising 172 c over-temperature shutdown hysteresis 22 c notes: 1. exceeding the absolute maxi mum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. devices are esd sensitive. handling precautions recommended. human body model, 1.5k ? in series with 100pf. 4. specification for packaged product only. 5. minimum on-time before automatic cycle skipping begins. see applications section.
micrel, inc. MIC25400 january 2011 6 m9999-020111-c typical characteristics 12v in efficiency vs. output current (09) 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0 0.0 0.5 1.0 1.5 2.0 output current (a) efficiency (%) 5vo 1.8vo 1.2vo 0.7vo 5v in efficiency vs. output current (09) 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0 0.0 0.5 1.0 1.5 2.0 output current (a) efficiency (%) 1.8vo 1.2vo 0.7vo i dd_off vs. input voltage 2 3 4 5 6 6 8 10 12 input voltage (v) idd_off (ma ) 25c -40c 85c i dd_on vs. input voltage 20 25 30 35 40 45 50 55 60 6 8 10 12 input voltage (v) idd_on (ma ) -40c 85c 25c enable threshold vs. input voltage 1.30 1.32 1.34 1.36 1.38 1.40 6 8 10 12 input voltage (v) enable threshold (v) -40c 85c 25c current limit threshold vs. input voltage 3.00 3.05 3.10 3.15 3.20 6 8 10 12 input voltage (v) current limit threshold (a) 25c output voltage v s. input voltage 3.20 3.25 3.30 3.35 6 8 10 12 input voltage (v) output voltage (v) -40c 85c 25c load regulation 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 0.0 0.5 1.0 1.5 2.0 output current(a) output voltage (v) v in = 12v v out = 3.3v -40c 85c 25c
micrel, inc. MIC25400 january 2011 7 m9999-020111-c functional characteristics
micrel, inc. MIC25400 january 2011 8 m9999-020111-c functional diagram pwm core MIC25400 block diagram
micrel, inc. MIC25400 january 2011 9 m9999-020111-c functional description the MIC25400 is a dual output, synchronous buck regulators. output regulation is performed using a fixed frequency, voltage mode control scheme. the fixed frequency clock drives the two sections 180 out of phase, which reduces input ripple current. oscillator an internal oscillator provides a clock signal to each of the two sides. the clock signals are 180 out of phase with the other. each phase is used to generate a ramp for the pwm comparator and a clock pulse that terminates the switching cycle. the MIC25400 oscillator frequency is nominally 1mhz. uvlo the uvlo monitors voltage on the v in pin. the circuit controls both regulators (side 1 and side 2). it disables the output drivers and discharges the en/dly capacitor when v in is below the uvlo threshold. as v in rises above the threshold, the internal high-side fet drivers and external low-side drives are enabled and the en/dly pins are released. a low impedance source should be used to supply input voltage to the MIC25400. when v in drops below the uvlo threshold and the outputs turn off, the change in input current will cause v in to slight rise. the output voltage will momentarily turn back on if the rise in v in is greater than the uvlo hysteresis. the preferred method is to use the en/dly pins, as shown in figure 1, for startup and shutdown of the outputs. this avoids the possibility of glitching during startup and shutdown. if an external control signal is not available, the circuit in figure 1a may be used to set a higher turn-on and turn-off threshold than the internal uvlo circuit. moreover, the hysteresis is adjustable and can accommodate a wider input source impedance range. please refer to the mic841 datasheet for additional information on selecting the resistor values. regulator/reference the internal regulator generates a pvdd pin voltage that powers the high-side mosfet and low-side gate drive circuits. it also generates an internal analog voltage, a vdd , which is used by the low level analog and digital sections. the a vdd voltage is also used by the bandgap to generate a nominal 700mv for the error amplifier reference. the output undervoltage and power good circuits use the bandgap for their references. the dropout of the inter nal regulator causes v pvdd to drop when v in is below 6v. when operating below 6v, the pvdd pin must be jumpered to v in . this bypasses the internal ldo and prevents v pvdd from dropping out. a 1f ceramic capacitor should be used to decouple v pvdd -to-ground. en/dly pin the en/dly pins are used to turn on, turn off and soft- start the outputs. the pins can be controlled with an open collector or open drain device as shown in figure 1. it must not be actively driven high or damage will result. when disabling the output with an external device, the enable pin turn-off time must be less than 1s. figure 1. enable and soft-start circuit figure 1a. adjustable uvlo startup circuit minimum output load when disabled when one output is disabled and the other enabled, then the disabled output requires a minimum output load to prevent its output voltage from rising. typically, a 2k ? load on the output will keep the output voltage below 100mv. the output setting voltage divider resistors may be used for the 2k ? load if the total resistance is set low enough. a separate output resistor should be used for lower output voltages since the voltage divider resistance becomes impractically low.
micrel, inc. MIC25400 january 2011 10 m9999-020111-c soft-start enable and soft-start waveforms are shown in figure 2. figure 2. soft-start timing diagram a capacitor, c ss , is connected to the en/dly pin. the c ss capacitor range is 4.7nf to 22nf. releasing the pin allows an internal current s ource to charge the capacitor. the delay between the en/dly pin release and when v out starts to rise can be calculated by the equation below. ss start threshold_ ss d i v c t = where: c ss is the soft-start capacitor. i ss is the internal soft-start current (200a nominal). v threshold_start is the en/dly pin voltage where the output starts to rise (1.35v nominal). the output voltage starts to rise when voltage on the en/dly pin reaches the star t threshold. the output voltage reaches regulation when the en/dly pin voltage reaches the end threshold. the output voltage rise time can be calculated by the equation below: ss start threshold_ end threshold_ ss d i ) v (v c t ? = where: v threshold_end is the en/dly pin voltage where the output reaches regulation. power good power good is an open drain signal that asserts when v out exceed the power good threshold. the circuit monitors the fb pin. the internal fet is turned on while the fb voltage is below the fb threshold. when voltage on the fb in exceeds the fb threshold, the fet is turned off. a pull-up resist or can be connected to p vdd or and external source. the external source voltage must not exceed the maximum rating of the pin. the pg pin can be connected to another regulator?s en/dly pin for sequencing of the outputs. a pull-up resistor is not used when the power good pin is connected to another regulators en/dly pin. output sequencing sequencing of the outputs is shown in figure 3. the power good pin is used to disable v out2 until the v out1 reaches regulation. sequencing waveforms are shown in figure 4. figure 3. output sequencing figure 4. output sequencing waveforms the MIC25400 must start up without a pre-biased output voltage. during start up, the MIC25400 pulls the output to ground if it is above 0v. this may cause the output to ring below ground and excessive voltage on the vsw node. a pre-bias condition can occur if the output is turned off then immediately turned back on before the output capacitor is discharged to ground. it is also possible that the output of the MIC25400 could be pulled up or pre-biased through parasit ic conduction paths from one supply rail to another in multiple voltage level ics like a fpga.
micrel, inc. MIC25400 january 2011 11 m9999-020111-c high-side drive the internal high-side drive circuit is designed to switch the internal n-channel mosfet. figure 5 shows a diagram of the high-side mosfet, gate drive and bootstrap circuit. d2 and c bst comprise the bootstrap circuit, which supplies drive voltage to the high-side mosfet. bootstrap capacitor c bst is charged through diode d2 when the low-side mosfet turns on and pulls the sw pin voltage-to-ground. when the high-side mosfet driver is turned on, energy from c bst charges the mosfet gate, turning it on. voltage on the sw pin increases to approximately v in . diode d2 is reversed biased and c bst flies high while maintaining gate voltage on the high-side mosfet. a resistor should be added in series with the bst1 and bst2 pins. this will slow down the turn-on time of the high-side mosfet while leaving the turn-off time unaffected. slowing down the mosfet risetime will reduce the turn-on overshoot at the switch node, which is important when operating with an input voltage close to the maximum operating voltage. the recommended capacitor for c bst is a 0.01f ceramic capacitor. the recommended value for r bst is 20 ? . figure 5. high-side drive circuitry low-side drive output the lsd pin is used to drive an external mosfet. this mosfet is driven out of phase with the internal high- side mosfet to conduct inductor current during the high-side mosfets off-time. circuitry internal to the regulator prevents short circuit ?shoot-through? current from flowing by preventing the high-side and low-side mosfets from conducting at the same time. the low-side mosfet gate voltage is supplied from v pvdd . turn off of the mosfet is accomplished by discharging the gate through the lsd pin. the return path is through the pgnd pin and back to the mosfet?s source pin. these circuit paths must be kept short to minimize noise. see the layout section of this datasheet for additional information. driving the low-side mosfet on and off dissipates power in the MIC25400 regulator. the power can be calculated by the equation below: s gs g driver f v q p = where: p driver is the power dissipated in the regulator by switching the mosfet on and off. q g is the total gate charge of the mosfet at v gs. v gs is the mosfet?s gate to source voltage which is equal to the voltage on p vdd. f s is the switching frequency of the regulator (1mhz nominal). dv/dt induced turn-on of the low-side mosfet as the high-side mosfet turns on, the rising dv/dt on the switch-node forces current through c gd of the low- side mosfet causing a glitch on its gate. figure 6 demonstrates the basic mechanism causing this issue. if the glitch on the gate is greater than the mosfet?s turn- on threshold, it may cause an unwanted turn-on of the low-side mosfet while the high-side mosfet is on. a short circuit between input and ground would momentarily occur, which lowers efficiency and increases power dissipation in both fets. additionally, turning on the low-side fet during the off-time could interfere with overcurrent sensing. figure 6. dv/dt induced turn-on of the low-side mosfet
micrel, inc. MIC25400 january 2011 12 m9999-020111-c the following steps can be taken to lower the gate drive impedance, minimize the dv/dt-induced current and lower the fet?s susceptibility to the induced glitch: ? chose a low-side mosfet with a high c gs /c gd ratio and a low internal gate resistance ? do not put a resistor between the lsd output and the gate. ? insure both the gate drive and return etch are short, low inductance connections. ? use a 4.5v v gs rated mosfet. its higher gate threshold voltage is more immune to glitches than a 2.5v or 3.3v rated mosfet. mosfets that are rated for operation at less than 4.5 v gs should not be used. ? add a resistor in series with the bst pin. this will slow down the turn-on time of the high-side mosfet while leaving the turn-off time unaffected. current limit the MIC25400 uses the sy nchronous (low-side) mosfet?s rds on to sense an over-current condition. the low-side mosfet is used because it displays lower parasitic oscillations after switching than the upper mosfet. additionally, it improves the accuracy and reduces false tripping at lower voltage outputs and narrow duty cycles since the off-time increases as duty- cycle decreases. figure 7 shows how over current protection is performed using the low-side mosfet. figure 7. over-current circuit inductor current, i l , flows from the lower mosfet source to the drain during the off-time, causing the drain voltage to become negative with respect to ground. this negative voltage is proportional to the instantaneous inductor current times the mosfet rds on . the low- side mosfet voltage becomes even more negative as the output current increases. the over-current circuit o perates by passing a known fixed current source through a resistor r cs . this sets up an offset voltage (i cs x r cs ) that is compared to the v ds of the low-side fet. when i sd (source-to-drain current) x rds on is equal to this voltage the soft-start circuit is reset and a hiccup current mode is initiated to protect the power supply and load from excessive current during short circuits. current limit calculations and maximum peak limit the current limit method require s careful selection of the inductor value and saturation current. if a short circuit occurs during the off-time, the overcurrent circuit will take up to a full cycle to detect the overcurrent once it exceed the overcurrent limit. the worst case occurs if the output current is 0a and a hard short is applied to the output. the short circuit causes the output voltage to fall, which increases the pulse width of the regulator. it may take three or four cycles for the current to build up in the inductor before current limit fo rces the part into hiccup mode. the wider pulse width generates a larger peak to peak inductor current which can saturate the inductor. for this reason, the minimum inductor value for the MIC25400 is 4.7h and the maximum peak current limit setpoint is 2.7a. the saturation current for each of these inductors should be at least 1.5a higher than the overcurrent limit setting. voltage setting components the regulator requires two external resistors to set the output voltage as shown in figure 8. figure 8. setting the output voltage the output voltage is determined by the equation below. ? ? ? ? ? ? + = r2 r1 1 v v ref out where: v ref is 0.7v nominal. if the voltage divider resistance is used to provide the minimum load (see en/dly section) then r1 should be low enough to provide the necessary impedance. once r1 is selected, r2 can be calculated with the following formula:
micrel, inc. MIC25400 january 2011 13 m9999-020111-c ref out ref v v r1 v r2 ? = minimum pulse width output voltage is regulated by adjusting the on-time pulse width of the high-side fet. this is accomplished by comparing the error amplifier output with a sawtooth waveform (see block diagram). the pulse width output of the comparator becomes smaller as the error amplifier voltage decreases. due to propagation delay and other circuit limitations, there is a minimum pulse width at the output of the comparator. if the error amplifier voltage drops any further, then the output of the comparator will be low. the pwm circuit will skip pulses if a smaller duty-cycle is required to maintain output voltage regulation. this effectively cuts the output frequency in half. thermal protection the internal temperature of the regulator is monitored to prevent damage to the device. both outputs are inhibited from switching if the over-temperature threshold is exceeded. hysteresis in the circuit allows the regulator to cool before turning back on.
micrel, inc. MIC25400 january 2011 14 m9999-020111-c application information component selection inductor the value of inductance is determined by the peak to peak inductor current. higher values of inductance reduce the inductor current ripple at the expense of a larger inductor. smaller inductance values allow faster response to output current transients but increase the output ripple voltage and require more output capacitance. the inductor value and saturation current are also controlled by the method of overcurrent limit used (see explanation in the previous section). the minimum value of inductance for the MIC25400 is 4.7h. the peak-to-peak ripple current may be calculated using the formula below. l f v ) v v ( v i s in(max) out in(max) out pp ? ? ? ? ? ? = where: i pp is the peak to peak inductor ripple current l is the value of inductance f s is the switching frequency of the regulator is the efficiency of the power supply efficiency values from the functional characteristics section can be use for these calculations. the peak inductor current in each channel is equal to the average output current plus one half of the peak-to-peak inductor ripple current. pp out pk i 0.5 i i + = the rms inductor current is used to calculate the i 2 r losses in the inductor. 2 out pp out inductor i i 3 1 1 i i rms ? ? ? ? ? ? ? ? + ? = maximizing efficiency requires the proper selection of core material and minimizing the winding resistance. the high frequency operation of the MIC25400 requires the use of ferrite materials. lower cost iron powder cores may be used but the increase in core loss will reduce the efficiency of the power supply. this is especially noticeable at low output power. the inductor winding resistance decreases effici ency at the higher output current levels. the winding resistance must be minimized although this usually comes at the expense of a larger inductor. the power dissipated in the inductor equals the sum of the core and copper losses. core loss information is usually available from the magnetics vendor. input capacitor a 10 f ceramic is suggested on each of the v in pins for bypassing. x5r or x7r dielectrics are recommended for the input capacitor. y5v dielectrics should not be used. besides losing most of their capacitance over temperature, they also be come resistive at high frequencies, which reduce their ability to filter out high frequency noise. output capacitor the MIC25400 regulator is designed for ceramic output capacitors although tantalum and aluminum electrolytic may also be used. output ripple voltage is determined by the magnitude of inductor current ripple, the output capacitor?s esr and the value of output capacitance. when using ceramic output capacitors, the primary contributor to output ripple is the value of capacitance. output ripple using ceramic capacitors may be calculated using the equation below: s out pp out f 2 v 8 i c ? ? ? where: v out is the peak-to-peak output voltage ripple i pp is the peak-to-peak ripple current as see by the capacitors f s is the switching frequency (1mhz nominal). when using tantalum or aluminum electrolytic capacitors, both the capacitance and esr contribute to output ripple. the total ripple is calculated below: [] 2 esr pp 2 s out pp out r i f 2 c 8 i v ? + ? ? ? ? ? ? ? ? ? = the output capacitor rms current is calculated below: 12 i i pp cout rms = the power dissipated in the output capacitors can be calculated by the equation below: ( ) esr 2 cout diss r i p rms cout ? = current limit resistor the current limit circuit responds to the peak inductor current flowing through the low-side fet. calculating the current setting resistor r cs should take into account the peak inductor current and the blanking delay of approximately 100ns.
micrel, inc. MIC25400 january 2011 15 m9999-020111-c figure 9. overcurrent waveform figure 9 shows the low-side mosfet current waveform. peak current is measured after a small delay. the equations used to calculate t he current limit resistor value are shown below: 2 i + i = i pp out pk l t v i i dly out pk oc ? ? = cs on oc cs i rds i r ? = where: i oc is the current limit set point l = inductor value t dly = current limit blanking time ~ 100ns i cs is the overcurrent pin s ense current (200a nominal) rds on is the on resistance of the low-side mosfet snubber a snubber is used to damp out high frequency ringing caused by parasitic inductance and capacitance in the buck converter circuit. figure 10 shows a simplified schematic of one of the buc k converter phases. stray capacitance consists mostly of the two mosfet?s output capacitance (c oss ). the stray inductance is mostly package and etch inductance. the arrows show the resonant current path when the high-side mosfet turns on. this ringing causes stress on the semiconductors in the circuit as well as increased emi. figure 10. output parasitics one method of reducing the ringing is to use a resistor to lower the q of the resonant circuit. the circuit in figure 11 shows an rc network connected between the switch node and ground. capacitor c s is used to block dc and minimize the power dissipation in the resistor. this capacitor value should be between five and ten times the parasitic capacitance of the mosfet c oss . a capacitor that is too small will have high impedance and prevent the resistor from damping the ri nging. a capacitor that is too large causes unnecessary power dissipation in the resistor, which lowers efficiency. the snubber components should be placed as close as possible to the low-side mosfet and/or external schottky diode since in contributes to most of the stray capacitance. placing the snubber too far from the fet or using an etch that is too long or too thin adds inductance to the snubber and diminishes its effectiveness. figure 11. snubber circuit
micrel, inc. MIC25400 january 2011 16 m9999-020111-c proper snubber design requires the parasitic inductance and capacitance be known. a method of determining these values and calculating the damping resistor value is outlined below. 1. measure the ringing frequency at the switch node which is determined by parasitic l p and c p . define this frequency as f 1 . 2. add a capacitor c s (normally at least 3 times as big as the c oss of the fet) from the switch node-to-ground and measure the new ringing frequency. define this new (lower) frequency as f 2 . l p and c p can now be solved using the values of f 1 , f 2 and c s . 3. add a resistor r s in series with c s to generate critical damping. step 1: first measure the ringing frequency on the switch node voltage when the high-side mosfet turns on. this ringing is charac terized by the equation: p p 1 c l 2 1 f ? = w here: c p and l p are the parasitic capacitance and inductance step 2: add a capacitor, c s , in parallel with the synchronous mosfet, q2. the capacitor value should be approximately 3 times the c oss of q2. measure the frequency of the switch node ringing, f 2. ) c (c l 2 1 f p s p 2 + ? = define f? as: 2 1 f f f' = combining the equations for f 1 , f 2 and f? to derive c p , the parasitic capacitance 1 ) (f 2 c c 2 ' s p ? ? = l p is solved by re-arranging the equation for f 1 . () 2 1 p 2 p ) (f c 2 1 l ? ? = step 3: calculate the damping resistor. critical damping occurs at q=1 1 c c l r 1 q p s p s = + = solving for r s p s p s c c l r + = figure 11 shows the snubber in the circuit and the damped switch node waveform. the snubber capacitor, cs, is charged and discharged each switching cycle. the energy stored in cs is dissipated by the snubber resistor, rs, two times per switching period. this power is calculated in the equation below. 2 in s s snubber v c f p ? ? = where: f s is the switching frequency for each phase v in is the dc input voltage low-side mosfet selection an external n-channel logic level power mosfet must be used for the low-side switch. the mosfet gate-to- source drive voltage of the MIC25400 is regulated by an internal 5v regulator. logic level mosfets, whose operation is specified at v gs = 4.5v must be used. use of mosfets with a lower specified v gs (such as 3.3v or 2.5v) are not recommended since the low threshold can cause them to turn on when the high-side fet is turning on. when operating the regulator below a 6v input, connect v dd to v in to prevent the v dd regulator from dropping out. total gate charge is the charge required to turn the mosfet on and off under specified operating conditions (v ds and v gs ). the gate charge is supplied by the regulator?s gate drive circuit. gate charge is a source of power dissipation in the regulator due to the high switching frequencies. at low output load this power dissipation is noticeable as a reduction in efficiency. the average current required to drive the mosfets is: s g dd f q i ? = ? ? = parameters that are important to mosfet selection are: ? voltage rating ? on resistance ? total gate charge
micrel, inc. MIC25400 january 2011 17 m9999-020111-c the mosfet is subjected to a v ds equal to the input voltage. a safety factor of 20% should be added to the v ds(max) of the mosfet to account for voltage spikes due to circuit parasitics. generally, 30v mosfets are recommended for all applications since lower v ds rated mosfets tend to have a v gs rating that is lower than the recommended 4.5v. rms current and mosfet power dissipation calculation switching loss in the low-side mosfet can be neglected since it is turned on and off at a v ds of 0v. the power dissipated in the mosfet is mostly conduction loss during the on-time (p conduction ). on 2 switch conduction rds i p rms ? = where: rds on is the on resistance of the mosfet switch. the rms value of the mosfet current is: ) 12 i (i d) (1 i 2 pp 2 out_max sw_rms + ? ? = where: d is the duty-cycle of the converter i pp is the inductor ripple current in out v v d ? = where: is the efficiency of the converter. external schottky diode a freewheeling diode in parallel with the low-side fet is needed to maintain continuous inductor current flow while both mosfets are turned off (dead-time). dead- time is necessary to prev ent current from flowing unimpeded through both mosfets. an external schottky diode is used to bypass the low-side mosfet?s parasitic body diode. an external diode improves efficiency due to its lower forward voltage drop as compared to the internal parasitic diode in the fet. it may also decrease high frequency noise because the schottky diode junction does not suffer from reverse recovery. an external schottky diode conducts at a lower forward voltage preventing the body diode in the mosfet from turning on. the lower forward voltage drop dissipates less power than the body diode. depending on the circuit components and operating conditions, an external schottky diode may give up to 1% improvement in efficiency. compensation the voltage regulation, filter and power stage section is shown in figure 12. the error amplifier regulates the output voltage and compensates the voltage regulation loop. it is a simplified type iii compensator utilizing two compensating zeros and two poles. figure 12 also shows the transfer function for each section. compensation is necessary to insure the control loop has adequate bandwidth and phase margin to properly respond to input voltage and output current transients. high gain at dc and low frequencies is needed for accurate output voltage regulation. attenuation near the switching frequency prevents switching frequency noise from interfering with the control loop. the output filter contains a complex double pole formed by the capacitor and inductor and a zero from the output capacitor and its esr. the transfer function of the filter is: 2 o s + o q s + 1 z s + 1 = gfilter(s) where: l c r q l c 1 o r c 1 z o o o esr o ? = ? = ? = the modulator gain is proportional to the input voltage and inversely proportional to the internal ramp voltage generated by the oscillator. the peak-peak ramp voltage is 1v. ? ? ? ? ? ? ? ? = ramp in v v gmod the output voltage divider attenuates v out and feeds it back to the error amplifier. the divider gain is: out ref v v r4 r1 r4 h = + =
micrel, inc. MIC25400 january 2011 18 m9999-020111-c figure 12. voltage loop and transfer functions the modulator, filter and voltage divider gains can be multiplied together to show the open loop gain of these parts. gmod h gfilter(s) gvd(s) ? ? = this transfer function is plotted in figure 13. at low frequency, the transfer function gain equals the modulator gain times the voltage divider gain. as the frequency increases toward the lc filter resonant frequency, the gain starts to peak. the increase in the gain?s amplitude equals q. just above the resonant frequency, the gain drops at a -40db/decade rate. the phase quickly drops from 0 to almost 180 before the phase boost of the zero brings it back up to -90. higher values of q will cause the pha se to drop quickly. in a well damped, low q system the phase will change more slowly. as the frequency approaches the zero frequency (f z ), formed by c o and its esr, then the slope of the gain curve changes from -40db/dec. to -20db/dec and the phase increases. the zero causes a 90 phase boost. ceramic capacitors, with their smaller values of capacitance and esr, push the zero and its phase boost out to higher frequencies, which allow the phase lag from the lc filter to drop closer to -180. the system will be close to being unstable if the overall open loop gain crosses 0db while the phase is close to -180. figure 13: gvd transfer function if the output capacitance and/or esr is high, the zero moves lower in frequency and helps to boost the phase, leading to a more stable system. error amplifier poles and zeros the error amplifier has internal poles and zeros that can be shifted in frequency with an external capacitor. the general form of the error amplifier compensation is shown in the equation below: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? + ? ? ? ? ? ? + = p2 s 1 p1 s 1 z2 s 1 z1 s 1 g gea(s) dc gvd transfer function -50 -40 -30 -20 -10 0 10 20 30 40 50 10 100 1000 10000 100000 1000000 frequency (hz) gain (db) -210 -180 -150 -120 -90 -60 -30 0 30 60 90 phase () gain phase v in = 12v v out = 1.8v c out = 20f l = 4.7h
micrel, inc. MIC25400 january 2011 19 m9999-020111-c the g dc is the dc gain of the error amplifier. it is internally set to 2500 (68db). as illustrated in figure 12, there are two compensating zeros. z1 is internally set with r3 and c3. the zero frequency is fixed at a nominal 16khz in the MIC25400. the second zero, z2, is set by the external capacitor, c2. for the MIC25400: c2 10 21 2 1 fz2 16khz c3 r3 2 1 fz1 100pf c3 100k r3 3 ? = = = = = the two compensating pole frequencies are shown below. c2 10 12 2 1 fp2 250hz fp1 3 ? = = fp2 and fz2 both depend on the value of c2 and are proportionally spaced in frequency with the zero at a lower frequency than the pole. this provides gain and phase boost in the control loop. voltage divider feedforward capacitor the capacitor across the upper voltage divider resistor boosts the gain and phase of the control loop by short circuiting the high-side resistor at higher frequencies. the capacitor and upper resistor form a zero at a lower frequency. the capacitor and parallel combination of upper and lower resistors form a pole at a higher frequency. this phase boost circuit is most effective at higher output voltages, where there is a larger attenuation from the voltage divider resistors. the general form of the feedforward circuit is shown below. ? ? ? ? ? ? ? ? + ? ? ? ? ? ? + + = p3 s 1 z3 s 1 r2 r1 r2 h(s) where: ? ? ? ? ? ? + = = r2 r1 r2 r1 c1 2 1 fp3 c1 r1 2 1 fz3 the total open loop transfer function is: h(s) gfilter(s) gmod gea(s) t(s) = the following tables list the recommended values of compensation and filter components for different output voltages. the output capacitors are ceramic. MIC25400 vin vout r1 r2 c2 c1 lo co 12v 1.0v 1k 2.32k 47pf 1.5nf 4.7h 22f 12v 1.2v 1k 1.4k 47pf 1.5nf 4.7h 22f 12v 1.4v 1k 1k 47pf 1.5nf 4.7h 22f 12v 1.8v 1k 634 47pf 1.5nf 4.7h 22f 12v 2.5v 1k 383 47pf 3.3nf 4.7h 22f 12v 3.3v 1k 274 68pf 3.3nf 4.7h 22f 12v 5.0v 1k 162 68pf 3.3nf 4.7h 22f
micrel, inc. MIC25400 january 2011 20 m9999-020111-c pcb layout guidelines warning!!! to minimize emi and output noise, follow these layout recommendations. pcb layout is critical to achieve reliable, stable and efficient performance. a ground plane is required to control emi and minimize the inductance in power, signal and return paths. the following guidelines should be followed to insure proper operation of the MIC25400 converter. ic ? place the ic and the external low-side mosfet close to the point of load (pol). ? use fat traces to route the input and output power lines. ? the exposed pad (ep) on the bottom of the ic must be connected to the ground. ? use several vias to connect the ep to the ground plane on layer 2. ? signal and power grounds should be kept separate and connected at only one location, the ep ground of the package. ? the following signals and their components should be decoupled or referenced to the power ground plane: vind1, vind2, pvdd, pgnd1, pgnd2, lsd1, and lsd2. ? these analog signals should be referenced or decoupled to the analog ground plane: vin, en/dly1, en/dly2, comp1, comp2, fb1, and fb2. ? place the overcurrent sense resistor close to the cs1 or cs2 pins. the trace coming from the switch node to this resistor has high dv/dt and should be routed away from other noise sensitive components and traces. avoid routing this trace under the inductor to prevent noise from coupling into the signal. input capacitor ? place the input capacitor next. ceramic capacitors must be placed between vind1 and pgnd1 and between vind2 and pgnd2. ? place the input capacitors on the same side of the board and as close to the ic and low-side mosfet as possible. ? keep both the vin and pgnd connections short. ? place several vias to the ground plane close to the input capacitor ground terminal, but not between the input capacitors and ic pins. ? use either x7r or x5r dielectric input capacitors. do not use y5v or z5u type capacitors. ? do not replace the ceramic input capacitor with any other type of capacitor. any type of capacitor can be placed in parallel with the input capacitor. ? if a tantalum input capacitor is placed in parallel with the input capacitor, it must be recommended for switching regulator applications and the operating voltage must be derated by 50%. ? in ?hot-plug? applications, a tantalum or electrolytic bypass capacitor must be used to limit the over- voltage spike seen on the input supply with power is suddenly applied. the value must be sufficiently large to prevent this voltage spike from exceeding the maximum voltage rating of the MIC25400. ? an additional tantalum or electrolytic bypass input capacitor of 22f or higher is required at the input power connection. inductor ? keep the inductor connection to the switch node (sw) short. ? do not route any digital or analog signal lines underneath or close to the inductor. ? keep the switch node (sw) away from the feedback (fb) pin. ? to minimize noise, place a ground plane underneath the inductor. output capacitor ? use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal. ? phase margin will change as the output capacitor value and esr changes. contact the factory if the output capacitor is different from what is shown in the bom. ? the feedback trace should be separate from the power trace and connected as close as possible to the output capacitor. sensing a long high current load trace can degrade the dc load regulation. ? if 0603 package ceramic output capacitors are used, then make sure that it has enough capacitance at the desired output voltage. please refer to the capacitor datasheet for more details. diode ? the external schottky diode is placed next to the low-side mosfet. ? the connection from the schottky diode?s anode to the input capacitors ground terminal must be as short as possible. ? the diode?s cathode connection to the switch node (sw) must be keep as short as possible.
micrel, inc. MIC25400 january 2011 21 m9999-020111-c rc snubber ? place the rc snubber on the same side of the board and as close as possible to the low-side mosfet. low-side mosfet ? low-side drive mosfet traces (lsd pin-to- mosfet gate pin) must be short and routed over a ground plane. the ground plane should be the connection between the mosfet source and pgnd. ? chose a low-side mosfet with a high cgs/cgd ratio and a low internal gate resistance to minimize the effect of dv/dt inducted turn-on. ? do not put a resistor between the lsd output and the gate. ? use a 4.5v vgs rated mosfet. its higher gate threshold voltage is more immune to glitches than a 2.5v or 3.3v rated mosfet. mosfets that are rated for operation at less than 4.5v gs should not be used. high-side mosfet ? add a 20 ohm resistor in series with the boost pin. this will slow down the turn-on time of the high-side mosfet while leaving the turn-off time unaffected.
micrel, inc. MIC25400 january 2011 22 m9999-020111-c MIC25400 evaluation board schematic
micrel, inc. MIC25400 january 2011 23 m9999-020111-c MIC25400 bill of materials item part number manufacturer description qty. c1 12103d226mat2a avx (1) ceramic capacitor, 22f, 25v, x5r 1 c2, c13 12063d106mat2a avx ceramic capacitor, 10f, 25v, x5r 2 c4, c10, c6, c9 06033d103mat2a avx ceramic capacitor, 10nf, 25v 4 c5 08056d225mat2a avx ceramic capacitor, 2.2f, 6.3v 1 c7 vj0603y680kxxmb vitramon (2) ceramic capacitor, 68pf, 50v, x7r 1 c8 vj0603y470kxxmb vitramon ceramic capacitor, 47pf, 50v, x7r 1 c11, c14 08056d226mat2a avx ceramic capacitor, 22f, 6.3v, x5r 2 c12 06033d105mat2a avx ceramic capacitor, 1f, 25v 1 c16 vj0603y332kxxmb vitramon ceramic capacitor, 3.3nf, 50v, x7r 1 c17 vj0603y152kxxmb vitramon ceramic capacitor, 1.5nf, 50v, x7r 1 c18, c19 vj0603y102kxxmb vitramon ceramic capacitor, 1nf, 50v, x7r 2 d1, d2 sd103bws vishay (2) schottky diode, 100ma, 30v 2 d3, d4 b0530w diodes. inc (3) schottky diode, 30v, 0.5a 2 l1, l2 dr74-4r7-r cooper (4) inductor, 4.7h, 4.3a 2 r1, r6 crcw06031001frt1 vishay dale (2) resistor, 1k (0603 size), 1% 4 r2 crcw06032740frt1 vishay dale resistor, 274 (0603 size), 1% 1 r3, r8 crcw06031002frt1 vishay dale resistor, 10k (0603 size), 1% 4 r4, r5 crcw06036040frt1 vishay dale resistor, 604 (0603 size), 1% 2 r7 crcw06031401frt1 vishay dale resistor, 1.4k (0603 size), 1% 1 r9, r10 crcw060320r0frt1 vishay dale resistor, 20 (0603 size), 1% 2 r12, r13 crcw06034992frt1 vishay dale resistor, 49.9k (0603 size), 1% 2 r15, r16, r17 crcw06030000frt1 vishay dale resistor, 0 ? (0603 size) 3 r20, r21 crcw08051r21frt1 vishay dale resistor, 1.21 ? (0805 size), 1% 2 q1, q2 fdn359an fairchild (5) mosfet 2 q3, q4 bss138 fairchild mosfet 2 u1 MIC25400yml micrel, inc. (6) 2a dual output pwm synchronous buck regulator ic 1 notes: 1. avx: www.avx.com 2. vishay: www.vishay.com 3. diodes inc.: www.diodes.com 4. cooper magnetics: www.cooperet.com 5. fairchild semiconductor: www.fairchildsemi.com 6. micrel, inc.: www.micrel.com
micrel, inc. MIC25400 january 2011 24 m9999-020111-c pcb layout recommendations top layer mid layer 1
micrel, inc. MIC25400 january 2011 25 m9999-020111-c mid layer 2 bottom layer
micrel, inc. MIC25400 january 2011 26 m9999-020111-c package information 24-pin 4mm x 4mm mlf ? (ml)
micrel, inc. MIC25400 january 2011 27 m9999-020111-c recommended land pattern 24-pin 4mm x 4mm mlf ? (ml) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fa x +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to t he accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for it s use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether expre ss, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, mi crel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including l iability or warranties relating to fitness for a particular purpose, merchantability, or infringement of an y patent, copyright or other intellectual p roperty right. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2009 micrel, incorporated.

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